The field of the invention is the formation of silicon insulator integrated circuits employing dual-gate technology.
The advantages of dual-gate transistors in SOI processing (e.g. improved short-channel effects and higher current drive) are well known.
Production of satisfactory dual-gate transistors using conventional processing techniques has not been achieved and the dominant approach for deep sub-micron lithography has involved vertical transistors.
The invention relates to a method of forming a dual-gate transistor that employs conventional processing to provide a back side gate that is self-aligned to the upper gate.
A feature of the invention is the use of a transfer method to generate marking features on the wafer backside comprising the formation of etch stop spacers on the edge of a gate stack and the etching of an alignment trench through the silicon device layer and through the buried oxide layer, so that deposition of an alignment layer on the bottom of the alignment trench provides a marker on the backside.
Another feature of the invention is etching the backside between the backside markers to provide a self-aligned backside aperture aligned with respect to the gate stack.